/*****************************************************************************
*   uart.h:  Header file for uart.c
*		ver 1.0	
******************************************************************************/
#include "me32g030.h"

#ifndef __ME32G030_DMA_H__
#define __ME32G030_DMA_H__
#pragma anon_unions
#ifdef __cplusplus
 extern "C" {
#endif
//DMA Data width
#define DMA_BYTE	0
#define DMA_HALF_WORD 	1 
#define DMA_WORD	2 
//DMA Address type
#define DMA_ADDR_INC	0
#define DMA_ADDR_FIXED 	3 
//DMA Channel
#define DMA_CHN_UART0_TX	0
#define DMA_CHN_UART0_RX 	1 
#define DMA_CHN_UART1_TX	2 
#define DMA_CHN_UART1_RX 	3 
#define DMA_CHN_UART2_TX	4 
#define DMA_CHN_UART2_RX 	5 
#define DMA_CHN_UART3_TX	6 
#define DMA_CHN_UART3_RX 	7 
#define DMA_CHN_CTIM0_MAT0	8 
#define DMA_CHN_CTIM0_MAT1	9 
#define DMA_CHN_CTIM1_MAT0	10 
#define DMA_CHN_CTIM1_MAT1	11 
#define DMA_CHN_ADC	12 
#define DMA_CHN_SPI0_TX	13 
#define DMA_CHN_SPI0_RX 	14 
#define DMA_CHN_SPI1_TX	15 
#define DMA_CHN_SPI1_RX 	16 
//DMA Priority
#define DMA_HIGH_PRIORITY	1 
#define DMA_INITIAL_PRIORITY 	0
//DMA Channel interrupt enable
#define DMA_CHN_INT_ENABLE	1 
#define DMA_CHN_INT_NOTENABLE 	0
typedef struct{
	__IO	uint32_t	SRC_END_PTR;
	__IO	uint32_t	DES_END_PTR;
  union {
    __IO uint32_t  CHNL_CTRL;                     /*!< Channel control register                                          */
    
    struct {
      __IO 	uint32_t cycleCtrl:3;				// 2:0 The operating mode of the DMA cycle
			__IO 	uint32_t RSVD0:1;					// 3 reserved
			__IO 	uint32_t nMinus1:10;				// 13:4  N DMA transfer
			__IO 	uint32_t rPower:4;					// 17:14 
			__IO 	uint32_t RSVD1:6;					// 23:18 reserved
			__IO 	uint32_t srcSize:2;					// 25:24 Set the bits to match the size of the source data
			__IO 	uint32_t srcInc:2;					// 27:26 Set the bits to control the source address increment
			__IO 	uint32_t dstSize:2;					// 29:28 Destination data size
			__IO 	uint32_t dstInc:2;					// 31:30 Destination address incrementuint32_t  MAP        :  2;               
    } CHNL_CTRL_b;                                /*!< BitSize                                                               */
  };

	__IO	uint32_t reserved;
}DMA_CHNL_CTRL_TypeDef;

#define DMA_START	(DMA->DMA_CFG_b .MASTER_EN=1)

void DMA_Init(DMA_CHNL_CTRL_TypeDef * dmactrl);
void DMA_Channel_Enable(uint8_t chn,uint8_t priority,uint8_t irqen);
void DMA_Channel_Disable(uint8_t chn);
void DMA_Channel_CFG(DMA_CHNL_CTRL_TypeDef* dmactrl,uint8_t chn,uint16_t nooftimes,uint8_t width,uint32_t srcaddr,uint32_t dstaddr,uint8_t srcaddrtype,uint32_t dstaddrtype);
void DMA_Clr_INT_Statu(uint8_t chn);
#ifdef __cplusplus
  }
#endif

#endif /* end __ME32G030_DMA_H */
/*****************************************************************************
**                            End Of File
******************************************************************************/
